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<title>kmi/arch/riscv64/config.h, branch master</title>
<subtitle>ACTIVE - Kernel with migrating threads as IPC</subtitle>
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<updated>2024-07-09T14:35:56Z</updated>
<entry>
<title>allow mapping null page</title>
<updated>2024-07-09T14:35:56Z</updated>
<author>
<name>Kimplul</name>
<email>kimi.h.kuparinen@gmail.com</email>
</author>
<published>2024-07-09T14:35:56Z</published>
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<id>urn:sha1:298636079d912d0936f8156a609fe74b839c547b</id>
<content type='text'>
+ User has to 'free' the 0 page before it becomes accessible to mapping.
  Probably worth noting that this is likely VERY niche and mainly
  concerns stuff like certain kinds of emulators that I'm still
  eons from implementing, but still.

  Unbacked pages can also be useful for some kinds of notifications,
  like 'if someone writes to this page, please report it to me with this
  ID' or whatever, I remember seeing some discussion about it somewhere
  but that's also not really relevant for the moment.

  Most significantly, at least with the current design,
  after the null page is freed it becomes available for use to regular req_mem()
  calls, so users should probably using locks around memory requests.
  That's probably a good idea anyway as internally the kernal has to
  lock the virtual memory, and without a scheduler it might cause
  threads to spin for a while in the kernel which is rather bad.
</content>
</entry>
<entry>
<title>smp now seems to work</title>
<updated>2024-07-07T04:00:43Z</updated>
<author>
<name>Kimplul</name>
<email>kimi.h.kuparinen@gmail.com</email>
</author>
<published>2024-07-07T04:00:43Z</published>
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<id>urn:sha1:122374c362ba8bb9082385da3c82e264ab594f15</id>
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+ Had some minor issues with a wraparound of size_t that effectively
  meant that some regions were allocated twice. Also, booting should be
  a bit more reliable now, turned out that the previous iteration of the
  booting was just accidentally working due to the kernel being placed
  'close enough' in RAM to where it was linked to. Fixed by allocating a
  vmem of O1 that maps the kernel to a 2MiB boundary at boot, pretty
  nifty.
</content>
</entry>
<entry>
<title>remove some unused macros</title>
<updated>2024-07-06T18:07:35Z</updated>
<author>
<name>Kimplul</name>
<email>kimi.h.kuparinen@gmail.com</email>
</author>
<published>2024-07-06T18:07:35Z</published>
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<content type='text'>
</content>
</entry>
<entry>
<title>prefer __riscv_xlen over riscv64</title>
<updated>2024-07-06T16:31:13Z</updated>
<author>
<name>Kimplul</name>
<email>kimi.h.kuparinen@gmail.com</email>
</author>
<published>2024-07-06T16:31:13Z</published>
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</content>
</entry>
<entry>
<title>move rpc stack handling to arch-specific code</title>
<updated>2023-10-09T13:15:06Z</updated>
<author>
<name>Kimplul</name>
<email>kimi.h.kuparinen@gmail.com</email>
</author>
<published>2023-10-09T11:57:18Z</published>
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<id>urn:sha1:9c9d589ea310f1290e4d6d2019fc8b51d9a86e42</id>
<content type='text'>
+ Fairly considerable speedup, as we don't have to look up the rpc pte
  every time separately, instead cacheing them. Adds an architecture
  specific limitation to total rpc stack size, though.
</content>
</entry>
<entry>
<title>visionfive2 boots</title>
<updated>2023-06-04T12:13:43Z</updated>
<author>
<name>Kimplul</name>
<email>kimi.h.kuparinen@gmail.com</email>
</author>
<published>2023-06-04T12:13:43Z</published>
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<id>urn:sha1:3dbd8c34176312b0bd3aba2309d284ac83181411</id>
<content type='text'>
+ Make 8250 serial driver more generic
+ Still TODO: write a tutorial on how to boot on the visionfive2
</content>
</entry>
<entry>
<title>arbitrary load address and RAM base detection</title>
<updated>2023-05-11T19:55:31Z</updated>
<author>
<name>Kimplul</name>
<email>kimi.h.kuparinen@gmail.com</email>
</author>
<published>2023-05-11T19:55:31Z</published>
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<content type='text'>
+ Both kind of go hand in hand, made sense to do both at the same time.

Some parts feel slightly hacky, the loader works by placing everything
on the stack and avoiding global values. Still, seems to work?
</content>
</entry>
<entry>
<title>update license stuff</title>
<updated>2023-05-01T19:02:49Z</updated>
<author>
<name>Kimplul</name>
<email>kimi.h.kuparinen@gmail.com</email>
</author>
<published>2023-05-01T19:02:49Z</published>
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</content>
</entry>
<entry>
<title>rename to kmi</title>
<updated>2023-04-30T14:06:02Z</updated>
<author>
<name>Kimplul</name>
<email>kimi.h.kuparinen@gmail.com</email>
</author>
<published>2023-04-30T14:06:02Z</published>
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<id>urn:sha1:ea5ebe0809fb31b9f125ac0689f706cc5f3f078f</id>
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</content>
</entry>
<entry>
<title>~1.3M ipc requests</title>
<updated>2022-11-13T05:28:52Z</updated>
<author>
<name>Kimplul</name>
<email>kimi.h.kuparinen@gmail.com</email>
</author>
<published>2022-11-13T05:28:52Z</published>
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<id>urn:sha1:b36e3b83b402ee054c319f0472b16a2bd64bba7e</id>
<content type='text'>
+ The secret is using gravestones. I'll have to write up full
  documentation for the feature but essentially riscv lets us encode
  whatever we want into page table entries, as long as they're not
  active. We use this to encode highest user address that is not a zero,
  in that all entries in the top level are either active or gravestones.
  When an active entry is removed, it is either a gravestone (if there
  are other active entries above it) or it starts a cascade of removing
  entries that have been previously removed

  Slight runtime overhead to page mapping, pretty major advantage in rpc
  calls. Feature will need to be tested more thorougly, and the init
  program is sort of a best scenario with just one top level userspace
  page table entry active at a time, leading to incredibly fast context
  switches.

  Current implementation limits a process' max virtual memory to 248 GiB
  (in Sv39), but I don't think the missing 8 GiB is that big of a deal.
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