From 452cab52de2107c1ce8c7eb0883ff80bb80ac76b Mon Sep 17 00:00:00 2001 From: Kimplul Date: Mon, 15 Dec 2025 01:25:53 +0200 Subject: add initial simt rv64 core --- src/cpu/riscv/simple_riscv64.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'src/cpu/riscv/simple_riscv64.c') diff --git a/src/cpu/riscv/simple_riscv64.c b/src/cpu/riscv/simple_riscv64.c index b2bdff6..fff9a62 100644 --- a/src/cpu/riscv/simple_riscv64.c +++ b/src/cpu/riscv/simple_riscv64.c @@ -661,6 +661,9 @@ static stat simple_riscv64_clock(struct simple_riscv64 *cpu) return ENOSUCH; } + if (ret != OK) + return ret; + if (cpu->ils.state == LDST_IDLE) { cpu->ils.pkt = create_packet(cpu->rcv + 64, cpu->pc, @@ -675,13 +678,16 @@ send: stat ret = SEND(cpu, cpu->imem, cpu->ils.pkt); if (ret == EBUSY) { cpu->ils.state = LDST_BLOCKED; - return ret; + return OK; } + if (ret != OK) + return ret; + cpu->ils.state = LDST_SENT; } - return ret; + return OK; } struct component *create_simple_riscv64(uint64_t rcv, uint64_t start_pc, -- cgit v1.3