From 452cab52de2107c1ce8c7eb0883ff80bb80ac76b Mon Sep 17 00:00:00 2001 From: Kimplul Date: Mon, 15 Dec 2025 01:25:53 +0200 Subject: add initial simt rv64 core --- include/gran/cpu/riscv/simt_riscv64.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 include/gran/cpu/riscv/simt_riscv64.h (limited to 'include') diff --git a/include/gran/cpu/riscv/simt_riscv64.h b/include/gran/cpu/riscv/simt_riscv64.h new file mode 100644 index 0000000..cd4f195 --- /dev/null +++ b/include/gran/cpu/riscv/simt_riscv64.h @@ -0,0 +1,24 @@ +#ifndef GRAN_SIMT_RISCV64_H +#define GRAN_SIMT_RISCV64_H + +#include +#include + +struct simt_riscv64_conf { + uint64_t data_rcv; + uint64_t inst_rcv; + uint64_t start_pc; + uint64_t num_lanes; +}; + +struct component *create_simt_riscv64( + struct simt_riscv64_conf conf, + struct component *imem, + struct component *dmem); + +struct component *simt_riscv64_data_intf(struct component *c); +struct component *simt_riscv64_inst_intf(struct component *c); + +void simt_riscv64_set_reg(struct component *c, size_t lane, size_t reg, uint64_t val); + +#endif /* GRAN_SIMT_RISCV64_H */ -- cgit v1.3