| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-12-24 | implement interconnect for simt cacheHEADmaster | Kimplul | |
| + Actual cache still missing, lol + Initial performance numbers aren't too promising compared to simt_riscv64 or even simple_mesh1d, but there's a somewhat increased latency due to registering inputs and the shared req logic which can likely be improved. Will have to dig into this a bit further | |||
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index : gran | |
| GOOFING OFF - A granular NoC simulator. | kimi.h.kuparinen+ttarv32@gmail.com |
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