From 2432cb953afa8ec3063307e3a788d7126b97318b Mon Sep 17 00:00:00 2001 From: Kimplul Date: Sun, 9 Jul 2023 15:11:13 +0300 Subject: rename from reg to val --- bcgen | 20 ++++++++++++-------- bcode.c | 29 +++++++++++++++++------------ bcode.h | 24 ++++++++++++++---------- 3 files changed, 43 insertions(+), 30 deletions(-) diff --git a/bcgen b/bcgen index 8c45345..0c9d5aa 100755 --- a/bcgen +++ b/bcgen @@ -4,6 +4,7 @@ import sys import pathlib def check_fmt(fmt): + # todo: should sign value be encoded in the registers? assert(len(fmt) == 6) assert(fmt[0] == '_' or fmt[0] == 'r') @@ -48,16 +49,16 @@ def gen_params(fmt): i = "" if fmt[5] == 'I': - i = ', gbreg_t imm' + i = ', ubcval_t imm' elif fmt[5] == 'D': - i = ', fbreg_t dimm' + i = ', fbcval_t dimm' return '(struct compile_state *cs' + r + i + ')' def gen_signature(name, fmt): ret = 'void ' if fmt[0] == 'r': - ret = 'breloc_t ' + ret = 'bcreloc_t ' n = 'select_' + name p = gen_params(fmt) @@ -83,7 +84,7 @@ def gen_enum_instance(f, name, r0, r1, r2, r3): f.write(enum + ',\n') class BCGen: - def __init__(self, r = 3, f = 3, head=''): + def __init__(self, r = 3, f = 3, extra='', head=''): self.r = r self.f = f @@ -109,12 +110,15 @@ class BCGen: with open('gen/select.h', 'w') as h: pass + with open('gen/extra.inc', 'w') as inc: + inc.write(extra) + with open('gen/head.inc', 'w') as inc: inc.write(head) with open('gen/regs.inc', 'w') as inc: - gregs = ['gbreg_t r' + str(i) + ' = 0;\n' for i in range(r)] - fregs = ['fbreg_t f' + str(i) + ' = 0;\n' for i in range(f)] + gregs = ['ubcval_t r' + str(i) + ' = 0;\n' for i in range(r)] + fregs = ['dbcval_t f' + str(i) + ' = 0;\n' for i in range(f)] for g in gregs: inc.write(g); @@ -132,7 +136,7 @@ class BCGen: p3 = param(fmt, 3) macro = '#define {}({}, {}, {}, {}) {}\n'.format( - name, p0, p1, p2, p3, body) + name, p0, p1, p2, p3, body.replace('\n', '')) f.write(macro) @@ -172,7 +176,7 @@ class BCGen: f.write(sign + '\n') f.write('{\nenum bcode_insn label = 0;\n') if fmt[0] == 'r': - f.write('breloc_t reloc = RELOC;\n') + f.write('bcreloc_t reloc = RELOC;\n') # kind of ugly but simplifies gen_select_instance a fair bit f.write('if (0) {}\n') diff --git a/bcode.c b/bcode.c index 1b0cba2..2f67250 100644 --- a/bcode.c +++ b/bcode.c @@ -6,12 +6,14 @@ #include "bcode.h" +#include "gen/head.inc" + enum bcode_insn { END, #include "gen/enum.inc" }; -static void append(struct compile_state *cs, enum bcode_insn label, breg_t imm) +static void append(struct compile_state *cs, enum bcode_insn label, bcval_t imm) { assert(cs->labels); @@ -32,19 +34,22 @@ static void append(struct compile_state *cs, enum bcode_insn label, breg_t imm) } #define RELOC cs->pc -#define PUSH_OP(label) append(cs, label, (breg_t){ .g = 0 }) -#define PUSH_IMM_OP(label, imm) append(cs, label, (breg_t){ .g = imm }) -#define PUSH_DIMM_OP(label, dimm) append(cs, label, (breg_t){ .f = dimm }) +#define PUSH_OP(label) append(cs, label, (bcval_t){ .r = 0 }) +#define PUSH_IMM_OP(label, imm) append(cs, label, (bcval_t){ .r = imm }) +#define PUSH_DIMM_OP(label, dimm) append(cs, label, (bcval_t){ .d = dimm }) #include "gen/select.inc" #include "gen/macro.inc" -#define IMM s.imm[pc].g -#define DIMM s.imm[pc].f +#define IMM s.imm[pc].r +#define SIMM s.imm[pc].s +#define FIMM s.imm[pc].f +#define DIMM s.imm[pc].d + #define NEXT_INSN goto *s.op[++pc] #define JUMP(i) goto *s.op[pc = (i)] -static gbreg_t _run(struct compile_state *cs, bool init) +static ubcval_t _run(struct compile_state *cs, bool init) { static void *labels[] = { [END] = &&end, @@ -56,8 +61,8 @@ static gbreg_t _run(struct compile_state *cs, bool init) return 0; } -#include "gen/head.inc" #include "gen/regs.inc" +#include "gen/extra.inc" const struct run_state s = cs->s; size_t pc = 0; @@ -69,7 +74,7 @@ end: /* we assume there's always at least one general register */ return r0; } -gbreg_t run(struct compile_state *cs) +ubcval_t run(struct compile_state *cs) { return _run(cs, false); } @@ -94,12 +99,12 @@ void end(struct compile_state *cs) PUSH_OP(END); } -breg_t label(struct compile_state *cs) +bcval_t label(struct compile_state *cs) { - return (breg_t){.g = cs->pc}; + return (bcval_t){.r = cs->pc}; } -void patch(struct compile_state *cs, breloc_t reloc, breg_t imm) +void patch(struct compile_state *cs, bcreloc_t reloc, bcval_t imm) { cs->s.imm[reloc] = imm; } diff --git a/bcode.h b/bcode.h index 730b8e7..a42f2f9 100644 --- a/bcode.h +++ b/bcode.h @@ -3,18 +3,22 @@ #include -typedef unsigned long gbreg_t; -typedef double fbreg_t; -typedef size_t breloc_t; +typedef unsigned long ubcval_t; +typedef signed long sbcval_t; +typedef float fbcval_t; +typedef double dbcval_t; +typedef size_t bcreloc_t; typedef union { - gbreg_t g; - fbreg_t f; -} breg_t; + ubcval_t r; + sbcval_t s; + fbcval_t f; + dbcval_t d; +} bcval_t; struct run_state { void* (*op); - breg_t *imm; + bcval_t *imm; }; struct compile_state { @@ -26,12 +30,12 @@ struct compile_state { #include "gen/select.h" -gbreg_t run(struct compile_state *cs); +ubcval_t run(struct compile_state *cs); void init(struct compile_state *cs); void end(struct compile_state *cs); void destroy(struct compile_state *cs); -breg_t label(struct compile_state *cs); -void patch(struct compile_state *cs, breloc_t reloc, breg_t imm); +bcval_t label(struct compile_state *cs); +void patch(struct compile_state *cs, bcreloc_t reloc, bcval_t imm); #endif /* BCGEN_BCODE_H */ -- cgit v1.3